The positive going transition (PGT) of the clock enables the switching of the output Q. Switching Example: Master-Slave J-K Flip-Flop The next step in making use of the versatile J-K flip-flop is to use four additional NAND gates to create the Master-Slave JK Flip Flop which has two gated SR flip flops used as latches in a way that suppresses the "racing". Modern ICs are so fast that this simple version of the J-K flip-flop is not practical (we put one together in the lab with an available 4-NAND chip and it was very unstable against racing). The timing pulse must be very short because a change in Q before the clock pulse goes off can drive the circuit into an oscillation called " racing". While this implementation of the J-K flip-flop with four NAND gates works in principle, there are problems that arise with the timing. This is what gives the toggling action when J=K=1. Note that the outputs feed back to the enabling NAND gates. HyperPhysics***** Electricity and magnetismĪ simplified version of the versatile J-K flip-flop. This toggle application finds extensive use in binary counters. It can also act as a T flip-flop to accomplish toggling action if J and K are tied together. It can perform the functions of the set/reset flip-flop and has the advantage that there are no ambiguous states. If J and K are both high at the clock edge then the output will toggle from one state to the other. If J and K are both low then no change occurs. The inputs are labeled J and K in honor of the inventor of the device, Jack Kilby. If J and K are different then the output Q takes the value of J at the next clock edge. It has the input-following character of the clocked D flip-flop but has two inputs,traditionally labeled J and K. On the other hand, if clock is returned low with J=0=K, the undetermined state will persist and this cannot be exited.The J-K flip-flop is the most versatile of the basic flip-flops. If the clock is set low with both J and K high, the output will continue to toggle but this can be exited by reclocking with opposing logic states at J and K. This can be exited by setting J and K at opposing states and setting CLK back to low. If simulation is started with clock (CLK) at high state, Q and NOTQ will toggle regardless of the state of J and K. If simulation is started with clock (CLK) at low state, Q and not Q will be at undetermined state and this cannot be exited. The 100 kΩ load resistors are not part of the Master-Slave J-K Flip-Flop, their purpose is to help initialize the output to known logic state. This results to a negative-edge-triggered master-slave J-K flip-flop. The circuit is an interconnection of a J-K latch and an S-R flip-flop in master-slave configuration.
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